1. Field of the Invention
The present invention relates to devices and methods that convert digital signals into corresponding analog signals (also known as digital-to-analog converters or DACs), and more particularly, to digital-to-analog converters based on current-steering architectures.
2. Background Art
Digital-to-analog converters are commonly employed in communications systems, and various audio and video applications. DACs intended for high-speed and high-accuracy applications are typically based on current-steering architectures. A conceptual view of a current-steering DAC is illustrated in FIG. 1. To convert an N-bit digital signal b0, b1 . . . bN−1 106 to an analog output 108, a current-steering DAC 100 may include K weighted current sources I0, I1 . . . IK−1 102. The current from the current sources 102 may be “steered” by M switches S0, S1, . . . SM−1 104. The digital signal 106 may control the operation of the switches 104. The number of current sources 102 and switches 104 needed to convert the N-bit digital signal 106 may depend upon the underlying architecture of a current-steering DAC. In general, neither K nor M need be equal to N, or to each other.
As shown in FIG. 1, the switches S0, S1, . . . SM−1 104 may steer the current output from the current sources either to ground 114 through an electrical connection 110 or through a load 112. The voltage, Vout, at the output terminal 108 may be measured across the load 112, shown as a resistor. In the current-steering DAC 100 shown in FIG. 1, the conversion from digital input 106 to analog output 108 may be performed by cumulatively adding the currents from those current sources 102 whose current is being steered towards the output terminal 112 through the switches 104 based on the digital input 106.
Design of a typical current-steering DAC may be based on a binary-weighted architecture, a thermometer-coded architecture, or a combination of these two architectures. DACs designed by combining binary-weighted and thermometer-coded architectures are typically referred to as segmented DACs.
In a binary-weighted architecture, each current source may be binary-weighted to represent its corresponding data bit, i.e., each current source may provide a current that may correspond to some power of two (e.g., 1; 2, 4, 8, 16, etc.). Thus, N current sources of increasing sizes may be used to convert an N-bit digital input signal into its corresponding analog output. Because each bit of the input digital signal 106 may correspond to a particular current source, the output of a current source 102 may be directly switched by its corresponding bit in the digital input 106. As a result, such a DAC may have reduced decoding needs, making such architectures area-effective. Reduced circuitry may also lead to other benefits, such as reduced cross-talk and reduced substrate noise. However, transistor matching requirements may become an issue in DACs that convert digital signals with a large number of bits. An increase in number of input bits implies an exponentially greater difference between the sizes of current source transistors for higher bits and for lower bits. A large difference in the size of current sources may increase the chances of errors in conversion due to mismatches in device sizing. The output of such a DAC may not be monotonic. Such problems may typically arise at major bit boundaries, for example, when a most significant bit (MSB) is turning “on” and all the least significant bits (LSBs) are turning “off.”
A thermometer-coded architecture may employ 2N−1 identical current sources to convert an N-bit binary signal. Unlike the binary-coded architecture, here an input binary bit in position N may correspond to 2N−1 current sources. And each current source may provide an output current that is equal to the amount of current that represents the LSB. Because all current sources may be identical, a thermometer-coded DAC may exhibit reduced conversion errors due to device mismatches and may have an increased likelihood of producing a monotonic output. However, the design complexity may increase significantly because of the exponential increase in the number of current sources. Increased design complexity may lead to other problems, such as a more complex decoding logic, a more complex layout, and increased cross-talk and substrate noise.
Because both the binary-weighted and the thermometer-coded architectures offer some advantages and disadvantages, for certain applications the two encoding schemes may be combined to form a segmented architecture. In a segmented architecture, some of the input bits may be converted according to the binary-weighted scheme while the remainder of the bits may be converted according to the thermometer-encoded scheme.
The current-steering DAC 100 may generally exhibit a higher power dissipation because the current sources 102 may remain “on” most the time when the DAC 100 is operating, whether or not the current is being “steered” to the load. Moreover, internal heat problems may be aggravated when many DACs are stacked together or a DAC has a high number of binary bits. High power dissipation may cause problems such as operation failure, performance degradation, low stability, and low reliability. Power dissipation is an even more critical problem because of increasing integration, shrinking geometries, and the need for DACs in portable applications that demand lower power consumption.